Book Description
Written for new users.

Explains the language through simple examples.

Explains the syntax of language using commonly-used design terminology.

Explains the behavioral style, the dataflow style, and structural style in detail.

Concepts of delay and timing are clearly explained.

Testbench writing is made easier by providing a number of examples.

Many hardware modeling examples have also been provided to make this an excellent reference. ... Read more

Customer Reviews (7)

A little disappointed
With such a high rating, I had hoped for something better.

If you are looking for a very introductory lesson on the workings of Verilog, this is for you. However if you are looking for something that will help you learn to write complex code, this is not it.

My biggest complaint is that this book needs to be hit pretty hard by an editor who actually understands Verilog enough to find the syntax errors and omissions in the example code. If this is supposed to be a "primer" all of the examples should be technically and syntactically correct, and they are not. I am able to find mistakes and this is my first foray into Verilog.

Also note: this does not teach anything about synthesizable code. That's another book, but the difference is never even mentioned.Almost everything in this book will help you learn how to write test benches for you synthesizable modules.

Not a very good book
Occasionally you see books that seem to be compiled by the author's lecture notes, this is one of them. It would still be ok if the notes were good, however this one isn't. It does it's job presenting the basics of Verilog, but on harder to understand concepts such as blocking/non-blocking procedural assignments and procedural continuous assignment, the author does an aweful job explaining it, which is where it counts the most. Similar problems appear throughout the book, and I can never understand why it has attained a four star rating, which is when I purchased it. If you can find a better book, go for it!

A must have book
While some might say that it's a beginners' book, you will
end up using this book the most. I have several Verilog
books in my cube at my work, but this is the book my
colleagues come very often to look up. This has excellent
and authentic descriptions of all Verilog language rules
and primitives. It also explains how and when to use
different Verilog constructs. I bet you will not regret
having this book.

Regurgitation of LRM
This book is basically a regurgitation of the language reference manual and really does not give the reader any insight into when and how to use particular language constructs. For example on page 148 the author discusses module ports and has an example of a port redeclaration, but he neglects to discuss why you would wish to redeclare a port as a wire. If you are learning Verilog because you are going to use it in an actual design look elsewhere.

Well Organised
This book is well organized.All the chapters are thoroughly written and hence easily understood by a beginner.I would personally refer this book both fora beginner and a practicing engineer. ... Read more

Book Description
The Verilog hardware description language provides the abilityto describe digital and analog systems for design concepts andimplementation. It was developed originally at Gateway Design andimplemented there. Now it is an open standard of IEEE and Open VerilogInternational and is supported by many tools and processes. TheComplete Verilog Book introduces the language and describes itin a comprehensive manner.
In The Complete Verilog Book, each feature of the language isdescribed using semantic introduction, syntax and examples. A chapteron semantics explains the basic concepts and algorithms that form thebasis of every evaluation and every sequence of evaluations thatultimately provides the meaning or full semantics of the language.
The Complete Verilog Book takes the approach that Verilog is notonly a simulation language or a synthesis language or a formal methodof describing design, but is a totality of all these and covers manyaspects not covered before but which are essential parts of any designprocess using Verilog. The Complete Verilog Book starts with atutorial introduction. It explains the data types in Verilog HDL, asthe object-oriented world knows that the language-constructs and datatypes are equally important parts of a language. The CompleteVerilog Book explains the three views, behavioral, RTL andstructural and then describes features in each of these views.
The Complete Verilog Book keeps the reader abreast of currentdevelopments in the Verilog world such as Verilog-A, cycle simulation,SD, and DCL, and uses IEEE 1364 syntax.
The Complete Verilog Book will be useful to all those who wantto learn Verilog HDL and to explore its various facets. ... Read more

Customer Reviews (3)

Good book, high price!
I liked the approach of describing the gate model, dataflow and behavioral model, all in one place, unlike other books. The text is mostly very clear.More state diagrams here and there may clarify. Unfortunatly PLI is not really covered. The CD rom contains only the code: other books provide a free (student version) vhdl simulator. At $ 135.00 + tax, the price is high, compared to other similar books covering the same topic.

A.G.- San Jose, CA

Good reference mediocre for learning.
The book has plenty of code samples, however, many of them have mistakes, making it difficult and sometimes frustrating to study the code.The explanations are not well written when compared to other books (Thomas andMoorby's), however there is some information that cannot be found in otherbooks.An excellent book except for the price and mistakes on nearly everypage.If you are already experienced in Verilog, this may be an excellentreference, however, if you are just learning, Thomas Moorby's "TheVerilog Hardware Description Language" is an excellent and highlyrecommended book.

a great book with almost everything for designers to referen
This book is really a worthwhile book to read and study for advanced topics of designs based on Verilog and Synopsys synthesis tools.The feature-rich topics and details of how the constructs of the designs aremade are quite clear and well-written for people involved.The only thingI'm concerned is the price seems to be way way too high to general reader,as it's $135 before tax.Hopefully the price can drop at least 40% less sothat everybody can buy it.regards,JKL, San Jose, Calif. ... Read more

Customer Reviews (26)

Surely there must be a better verilog book out there
Here are my complaints with the book:

1. Poor organization -- While it does contain a fairly complete description of Verilog, it's not a very useful description. Reading this book is like reading the Tax Act - all the information is there somewhere, but good luck trying to find it.

2. Poor index -- As a reference, this book is pretty much useless because it lacks a good index. Many items discussed in the book are _not_ in the index. So you can never find that thing that you vaguely remember reading about last month. And you cannot find the answer to a simple question quickly.

3. Lack of practical examples -- For a chip designer or verifier, this book is more or less useless. Although it claims to be "A Guide to Digital Design and Synthesis", there is only one brief chapter on synthesis, and it is severely lacking (a mere 40 pages out of 450). He doesn't even demonstrate how to code a flip-flop with an asynchronous reset. When it comes to practical usage, you're better off searching the web, or reading the source code for the openrisc processor, or something written by an experienced co-worker, or even just reading chapters 11 and 12 of "Application Specific Integrated Circuits" by Michael Smith (also available online I think).

4. Expensive -- I recommend you save your money and just use on-line resources to learn Verilog. None of these on-line resources are great, but at least you will be getting your money's worth, which is more than I can say about this book.

Awful reference source
I used this book to learn Verilog and if you read it from beginning to end, you might learn the gist of the language...but that's it.The book is virtually useless as any kind of reference source.The index is almost unusable (if you want to learn about the keywords "fork" or "join", for example, good luck.They aren't even listed in the index, along with just about everything else).Descriptions of how the language works are cryptic and overly brief, though the examples are sometimes helpful.

I seldom write reviews of books, but this one has annoyed me so much that I felt compelled to do so.

All in all, it's better than no book at all, but not much better.

Great coverage of Verilog language
Very comprehensive text about the Verilog language, covering the various aspects of the language. The text is clear and well organized. The exercises at the end of the chapter helped me a lot in the learning process. The simulator included is very simnple and all examples in the book run flawlessly. A few things I did not like: the few mistakes in the text and code could have been easily caught by any careful reviewer, the lack of a more detailed example to show the usage of the various constructs in a real world Verilog design and hints about how to build synthesizable Verilog programs. I have enjoyed the author's style and recommend the book for any person who wants to learn Verilog, including other software engineers like myself who want to understand some HDL basics.

Good explanations but not for reference
I read the book; it is a good one for reader to catch the idea quickly. But to use it as a reference book might not be a good idea. The topic organization is divided into basic usage section and advanced technique section, and kind of hard to locate for a certain issue. However, it is still worthy of reading as a beginner. The most things I like this book is it use example(s) to explain the concept.

an easy language
The author offers more than just a detailing of the various parts of the Verilog language. He also covers extra features that enhance what you can do in Verilog for the purposes of modelling or analysis.

Perhaps the most important aspect is how to divide your design into modules. A top-down approach that can greatly aid reducing the complexity of the original problem. Also, constructing modules helps in the testing of the full circuit, by being able to design in tests of each module. If you have a background in software, then you will recognise this factorisation into modules as very akin to traditional software design.

For the student, the chapters have numerous problem sets that let you tackle the language. The text shows that Verilog is actually a fairly simple language, as computer languages do. Those of you who have programmed in other languages should encounter no serious problems with Verilog. ... Read more

Book Description
Principles of Verilog PLI is a `how to do' text onVerilog Programming Language Interface. The primary focus of the bookis on how to use PLI for problem solving. Both PLI 1.0 and PLI 2.0 arecovered. Particular emphasis has been put on adopting a genericstep-by-step approach to create a fully functional PLI code. Numerousexamples were carefully selected so that a variety of problems can besolved through ther use. A separate chapter on Bus Functional Model(BFM), one of the most widely used commercial applications of PLI, isincluded.
Principles of Verilog PLI is written for the professionalengineer who uses Verilog for ASIC design and verification.
Principles of Verilog PLI will be also of interest to studentswho are learning Verilog. ... Read more

Customer Reviews (5)

Multiple instances of same module containing a PLI call
Swapnajit, First congratulations on your book. This is a major progress in documenting and demistifying the PLI mechanism. The examples of your bookare excelent starting points.I grade myself as a medium expert in PLI. SoI am still waiting for a second, higher-class book to cover more advancedtopics. One of them is multiple instances of a module containing a PLI calland hence multiple instances of the same Ccode. My problems started whendata belonging to one instance interfered with data belonging to otherinstance. Actually I would like to see in your next book or revision sometips about this issue. In general some good PLI coding practices would bewellcomed. I also encountered race conditions in which the order of the PLIC routines calling influenced the behaviour, and hence not reliable.Thesecond subject I liked very much in your book is the communication betweenverilog processes. The actual application I hoped to be able to put to workis a kind of "software -hardware coverification" (for poors).Actually I have a PLI that mimics the bus activity of a CPU and now I wantit to run real C program. I would like that C program to run in a differentenvironment from the simulator, and only on CPU-read and CPU-write toenable a handshake mechanism. Since I am not a TCP IP socket expert Idropped the effort after a couple of days, when I reached the notoriousdeadlock of both processes waiting for one another... I would also like tosee in the next revision tips about debugging, and some NOT-TO-DOs. Iencountered some problems when using parameters in verilog that are passedalso to PLI's. I think you may add some words about this as well. All inall I enjoyed the book. Keep up ! Last but not least thank you for youranswers to my e-mails regarding the PLI stuff. I also appreciate youractivity in the comp.lang.verilog forum.

Fair at best.Other books are better.
Save your money and buy the Stuart Sutherland book "The Verilog PLI Handbook"ISBN 0-7923-8489-X it's much better.I have both.

Essential for anybody seeking to learn Verilog PLI
Absolutely essential for anybody seeking to learn the fundamentals of Verilog PLI. Various usagesof Verilog PLI including different types of library functions :access and utility routines as well as VPIs areextensively covered with numerous detailed examples. The reviewer found thebook to be a well read and lucidly written.

A very useful book
This is a very useful book for those who want to learn intricacies of Verilog PLI without spending hours on reading manuals. The best part of this book that I liked is its set of examples - almost all functions andtheir uses have been explained with an easy-to-understand example. Most ofthese examples are presented in their bare-bone structure so that users cancustomize them according to their needs. A more careful look at theexamples would reveal that the author has subtly divided them into twocategories - one for the beginners and the other for the more advancedusers.

Overall, I will recommend this book to anybody who wants to learnVerilog PLI.

Excellent book!
I found the book very useful because of the lots of examples, informal presentation(helps beginners), seperate chapter on BFM, coverage for both PLI1.0 and PLI2.0 and exercise (Self-check) to measure progress.

I am ofthe opinion that this book would be a worthy investment for a quick startin hardware design. ... Read more

Book Description
The first edition of Principles of Verifiable RTL Designoffered a common sense method for simplifying and unifying assertionspecification by creating a set of predefined specification modulesthat could be instantiated within the designer's RTL. Since therelease of the first edition, an entire industry-wide initiative forassertion specification has emerged based on ideas presented in thefirst edition. This initiative, known as the Open Verification LibraryInitiative (www.verificationlib.org), provides an assertion interfacestandard that enables the design engineer to capture many interestingproperties of the design and precludes the need to introduce new HDLconstructs (i.e., extensions to Verilog are not required).Furthermore, this standard enables the design engineer to `specifyonce,' then target the same RTL assertion specification over multipleverification processes, such as traditional simulation, semi-formaland formal verification tools. The Open Verification LibraryInitiative is an empowering technology that will benefit design andverification engineers while providing unity to the EDA community(e.g., providers of testbench generation tools, traditionalsimulators, commercial assertion checking support tools, symbolicsimulation, and semi-formal and formal verification tools).
The second edition of Principles of Verifiable RTL Designexpands the discussion of assertion specification by including a newchapter entitled `Coverage, Events and Assertions'. All assertionsexampled are aligned with the Open Verification Library Initiativeproposed standard. Furthermore, the second edition provides expandeddiscussions on the following topics:

• start-upverification;
• the place for 4-state simulation;
• raceconditions;
• RTL-style-synthesizable RTL (unambiguous mapping togates);
• more `bad stuff'.

Customer Reviews (3)

has practical tips, is shallow in giving understanding
The chapter on bad stuff is useful and practical, even though it repeats parts of previous chapters. The chapter on assertion based verification is practical too. Some of the reasonings on use of "x" may be debatable. For example, the authors argued that two-state detects more problems than x injection, based on their experiences. In the text, an example was given. What the example illustrates is NOT the inherent problems with x injection but a truly bad style of coding to detect x. Thus, the example is misleading.

The chapter on formal verification is a cheat-sheet user manual for some commercial tools. It gives a couple of lines of math symbols about formal verification theory, without explanation whatsoever. In general, this chapter is too shallow for understanding the ideas behind formal verification.

In many places, the book just lists the benefits of some practices without giving reasons and details about the practices. It's very frustrating to have the thought hung in mid-air.

So if you are looking for a partial collection of tips to avoid simulation based verification problems, this book is a start. If you want a more in-depth and complete understanding in verifiable RTL design, find other books.

An excellent book for advanced users
This book presents principles drawn from very large scale designs, like microprocessor.If you are looking for a book describing testbench implementation, another book, "Writing testbenches functional verification of hdl models", is more suitable.If you are working on very large scale and complex design verification, this book will be very helpful.The discussion of simulation optimization, X/Z state, X/Zero/Random initialization during simulation is very insightful.

Out of the ordinary
If you are looking for another book describing the Verilog Language Reference Manual then this book is not for you.If, however, to are looking for an excellent set of principles to build a design andverification philosophy then I highly recommend this book.The authorshave produced an RTL centric view of design emphasizing the verificationprocess. They argue that synthesis productivity gains have now placed theverification process in the critical path and that equal attention shouldbe giving to coding for verification as is currently given to coding forsynthesis.The chapter I particularly enjoyed, entitled "BadStuff," provides an excellent discussion with examples on codingstyles that hinder efficient verification. The author's discussion of theproblems with the use of X at the RT-level, due to X-state pessimism andoptimism, and the need for 2-state RTL simulation is enlightening. ... Read more

Book Description
The Designer's Guide to Verilog-AMS presents Verilog-AMS, the new analog and mixed-signal extensions to the widely used Verilog hardware description language.
It starts by describing a rigorous and proven top-down design methodology. Top-down design is widely seen as the key to being able to design very large and complex mixed-signal circuits and it is enabled by Verilog-AMS. Verilog-A and Verilog-AMS are then introduced without assuming that the reader has a background in behavioral modeling. Finally, it includes a comprehensive reference guide for the language.
The Designer's Guide to Verilog-AMS is extensively cross-referenced and indexed, making it an ideal reference for both Verilog-A and Verilog-AMS. A companion website, www.designers-guide.com, provides electronic copies of all the models used in this book, a library of user-contributed models, a discussion forum, additional documents on simulation and modeling, and other useful material.
The Designer's Guide to Verilog-AMS is written for analog and mixed-signal designers, particularly those designing larger and more complex circuits. ... Read more

Customer Reviews (4)

Verilog AMS
I design ADCs. I bought this book because we the tool became available to me at work. My first impression was underwhelming. However, as a reference book I have found it useful, and one of my associates borrows it also.

This is about all that is available. It is useful.

An introduction to Verilog AMS
I am new to verilog A and even newer to Verilog AMS.I thought the book was a reasonable introduction to the language, but I prefer a longer text with more content.The book is only of moderate length and expensive as seems to be typical of Kluwer texts.There are also some spots where clarity, at least to myself, was lacking.A user will need the Verilog AMS license from Cadence to use this language.Lacking such a license, I was never able to apply the mixed signal info from the text.For the pure Verilog A user who is doing only analog and not mixed signal sims, this book may not offer an advantage over Fitzpatrick's book even though it is newer.For the practicing engineer, this text is a far better way of getting introduced to Verilog AMS than Cadence's cryptic documentation.

Excellent introduction to the language & excelent reference
This book is currently the only up-to-date reference book for Verilog-A and Verilog-AMS (the book by Fitzpatrick is very incomplete and way out of date).

It introduces the language by using a series of relatively simple yet useful examples. In doing so it gets you up and running quickly and then builds your knowledge of the language. It takes you through Verilog-A in some depth, then presents enough Verilog-HDL (the digital subset) to give analog designers a workable understanding of Verilog, and then covers Verilog-AMS in depth.

The book has one chapter that acts as a complete reference for the manual for VerilogA/MS and and excellent index. I use the book as a reference as I write models and can always find what I am looking for very quickly.

In short, I recommend it whole-heartily. It is an essential book for anyone that uses Verilog-A or Verilog-AMS.

-August

Pointer to more information
I am one of the authors of this book and I wanted to let you know that if you wished to find out more about it before your ordered it, you can go to its home page, which can be found at http://www.designers-guide.com/Books/. It contains considerably more information about the book, including excerpts.

Amazon would not allow me to post this message to you without giving the book a star rating. So I did my best to provide an unbiased opinion ;-).

-Ken ... Read more

Customer Reviews (13)

The Book's Title fits
Ken's book contains many helpfull hints for the day to day FPGA design. It explains very well the pitfalls you will be trapped by and answers e.g. questions like what is actually is the difference between blocking and non-blocking assignment.

Sloppy and incoherent, some useful information
This book addresses how to use Verilog to create working FPGA designs. It touches on topics such as clocking, implementation of specific types of logic blocks, and design flow. The examples are written using Verilog.

The writing is sloppy, the organization is incoherent, and the explanations are incomplete. A reader may find the book worthwhile if: he or she already knows most of the material presented, has a few problems that are addressed by the book, can find the discussion of that problem in the book, and the discussion is one of those that is complete and accurate. Otherwise, the book is a waste of time and money.

The author assumes that the reader is familiar with digital logic design, the basics of Verilog, and the basics of FPGA and ASIC design. The book discusses strategies for dealing with practical problems. Unfortunately, the strategies are presented in a disorganized manner, with explanations that are poorly thought out and too incomplete to use.

The first chapter introduces Verilog design for FPGA synthesis. The contents of the chapter are a mish-mash. It is hard to tell what you are supposed to know after reading the chapter that you didn't have to know before reading it. The chapter isn't a quick description of Verilog, because it leaves out most Verilog syntax that you have to know (for example, vectors). The chapter isn't limited to describing what subset of Verilog is synthesizable, because it has detailed but incomplete descriptions of random Verilog topics such as number formats (eg. 1'b0). There are even pages of tables showing boolean logic truth tables for basic logic primitives such as and, or, and xor.

The second chapter is a discussion of how FPGAs are implemented, and the effect that this has on synthesis. For example, clocking strategies are discussed, with some references to differences between FPGAs and ASICs. There is also a discussion of how a logic synthesizer might operate. A few other topics are thrown in, such as a discussion of DeMorgan's theorems. The chapter is too incomplete and poorly-written to be of much practical use. For example, although there is a description of how logic elements can be built out of transistors (including simplified schematics of one possible approach), there is no serious discussion of what implications this has. The book is about FPGA design, but the section on how logic functions are implemented in most FPGAs (as lookup tables) does not describe this in any detail.

The third and fourth chapters, regarding implementing specific digital circuits in FPGAs using Verilog, are potentially the most useful. The concept of the chapters is that they show how to write Verilog for useful functions in a way that can be synthesized well into FPGAs. If the chapters had been well organized and complete, the book would have been worth buying just for them. However, the chapters are as poorly-written as the rest of the book. Large sections are taken up with a discussion of writing adders and subtractors - showing that there is little point in doing so yourself instead of letting the synthesizer do it. However, the discussion of finite state machines - an important topic - covers state machines implemented using binary or Gray codes to represent states. The discussion of 'one-hot' state machines (frequently used in practice in FPGAs) is incomplete, describing only the problems, but failing to present an example that works (or any example at all). Similarly, the discussion of FIFOs (important to synchronize portions of large designs) is limited to a few notes about problems, without a single example. This is surprising, because the book emphasizes that the designer must solve clocking and synchronization problems across large designs, yet solutions to this problem (such as FIFOs) are not described.

The second half of the book, mainly chapters 5 through 8, describe how to use specific Verilog tools. The chapters are useless reiterations of documentation for obsolete versions of specific tools.

Chapter 9, the last chapter, is about designing for ASIC conversion. This could have been a useful chapter, because it covers an important topic.

All in all, I think this is a book to avoid.

On the positive side, this book seems to have fewer obvious editing errors than most other 'instant books'. Also, the typesetting is fairly normal, with reasonable sized text and reasonable margins. The organization and contents of the section headings is hard to understand, but that is a reflection of the disorganization of the book, rather than a problem with the design. The only significant problem I had with the graphic design of the book relates to the graphics, primarily schematics with some screen captures. The scaling is not uniform, so in a single explanation, the size of a schematic symbol and associated label might vary from graphic to graphic. However, this is a minor problem.

It scratched my itch....
This book fit nicely in the gap I noticed between books on digital design with Verilog that were written from a structured academic standpoint and product specific user manuals and application notes.To learn effective FPGA design from books one would desire to have this book along with the other two; lacking "Real World FPGA Design" one would have to ask colleagues lots of questions and learn the rest the hard way.

I am using this book as I 'retool' as a FPGA Digital Design Engineer since full-custom design jobs here are drying up since few companies can afford the investment of time and money to bring custom devices to market.I wish there was a book like this for the classic chip design world that I could wave at the newbie system and digital designers that wanted me to add an 8 input NOR gate to the library that could drive a fanout of 50 loads 10 mm away.

Verilog is a many-faceted gem; I have been using it since the early 90's, albeit at the switch and structural level.This book is useful to me as I learn to design in Verilog at greater level of abstraction and it differs from other texts I have found in that it does not lose sight of the lower-level 'gotchas'.

The only thing that keeps me from giving this book my highest rating is that there are some errors that do need correcting;the URL listed in another review here remedies that problem.

Good writing style
I'm an analog design engineer with over 20 years of experience in industry.I want to add FPGA's to my bag of tricks, and I ran across Mr. Coffman's book via a search with Google.My book arrived a week ago and I am finding it to be just the kind of book I have been looking for.He has a good writing style, very easy to follow.I plan to invest many hours working through his examples with the included software.I have read other reviews of this book at this Amazon site.Some people are looking for an academic book on Verilog.Others are looking for a book that will teach them Verilog without spending the time programming and simulating (ie learning without doing homework).If you fall into either of these groups, this book is not for you.However, if you are an experienced engineer looking to learn about Verilog and VHDL through honest study and experimenting, then Mr. Coffman's book is an excellent choice to guide you through this process with a focus on the "real world".You also may find yourself chuckling at some of his commentary on the way

Excellent jump-start book for engineers!
Anyone who understands C/pascal is going to love Ken's book.It's the perfect reference to sit next to your keyboard for a quick hands-on reference!

Ken taught me in 1 minute how to create an array of cells in an FPGA simply via the TOC!In another minute I was implementing static-keys into a ROM'd lookup table.

It could not have been easier.

*Anyone trying to implement algorithms in Verilog should by this book* ... Read more

Book Description
Hardware Description Languages (HDLs) use statements, like programming language statements, in order to define, simulate, synthesize, and layout hardware. One of the main HDLs is Verilog, a widely used and standardized language. Verilog can be used to design anything from the most complex ASIC to the least complex PAL. As ASICs and FPGAs become more complex, HDLs become a necessity for their design. This course teaches how to use Verilog to design and simulate hardware. It begins by explaining the benefits of HDLs over other design entry methods, including its ability to model different levels of abstraction, its reusability, and documentability. Next, the syntax of the Verilog language is explained in detail. By the end of the course, you will be able to design and simulate real hardware using Verilog. The course includes the study guide, final exam, the textbook Verilog Designer's Library (Prentice Hall, 1998) and one CD-ROM containing simulation software from Simucad, synthesis software from Synopsys and all of the code examples from the book. Upon successful completion the student receives 8 CEUs and a Certificate of Educational Achievement from the Institute of Electrical and Electronics Engineers. ... Read more

Book Description
Contributions on UML address the application of UML in the specification of embedded HW/SW systems. C-Based System Design embraces the modeling of operating systems, modeling with different models of computation, generation of test patterns, and experiences from case studies with SystemC. Analog and Mixed-Signal Systems covers rules for solving general modeling problems in VHDL-AMS, modeling of multi-nature systems, synthesis, and modeling of Mixed-Signal Systems with SystemC. Languages for formal methods are addressed by contributions on formal specification and refinement of hybrid, embedded and real-time stems.
Together with articles on new languages such as SystemVerilog and Software Engineering in Automotive Systems the contributions selected for this book embrace all aspects of languages and models for specification, design, modeling and verification of systems. Therefore, the book gives an excellent overview of the actual state-of-the-art and the latest research results. ... Read more

Customer Reviews (1)

Good to have it
It is a handy book when you want to design a logical ciruit.It is mucheasier to simulate a circuit base on a simulation criteria than to build acircuit and experonce on that.

the book helps to learn about thesimulation concepts and much more... ... Read more

Book Description

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology.

Customer Reviews (1)

High-level, abstract approach and guidelines for the *experienced* Verification engineer
The book's title is a bit misleading.It does NOT teach you Systemverilog (for Verification) -- there is a separate book by Chris Spear ("Systemverilog for Verification") sold by the same publisher that focuses more on Systemverilog syntax and language features.This book is NOT a tutorial (i.e. beginner's guide) on how to write testbenches -- although it does go through the basic concepts, objectives, and challenges in writing maintainable/re-usable testbench environments, most of the textbook examples are too cryptic/advanced for an entry-level engineer.

So then, what does this book focus on?Well, the book focuses on general guidelines to writing re-usuable, high-level testbenches.The author uses Systemverilog as the language to communicate his concepts, but as I said before, the book does NOT teach you Systemverilog.(To the author's credit, he is very upfront about that in foreward/intro section.)

Who should read it:
Experienced verification engineers with a basic understanding of Systemverilog (and why it's superior to Verilog), who want some ideas/examples of how to deploy Systemverilog's advanced features (like classes, structs, random vars) in a verification environment.

What I liked:
The use of classes to encapsulate bus-functional-models (BFMs), how to create and manage variations of a basic BFM (using extended/derived classes), etc.He also shows how to combine randomization with classes, to create random stimulus-sequences.

What could have been improved:
I was hoping the book would cover SVA (systemverilog assertions) in greater depth, but I guess there are other books for that.He also superficially mentions "configurations" -- that is a feature in Verilog-2001 and VHDL-93.The book should have covered that in more depth (even though it's not a new Systemverilog feature), as it pertains to testcase management and organization.

What you should have:
You need a good background and experience in ASIC/RTL-verification -- this book is not an introduction to testbench concepts, or the Systemverilog language!You need to know some Systemverilog language, so either have a different book (like Chris Spear's "Systemverilog for Verification"), or the official IEEE Systemverilog 1800-2005 LRM next to your side.Though not necessary, it's helpful to have a basic understanding about object-oriented programming, because the examples in the book use Systemverilog's classes (and inheritance) to illustrate a lot of points.Object-oriented concepts would otherwise be foreign to most engineers working in the hardware field.

Ohter notes:
The book makes numerous references to the VMM (Verilog Methodology Manual), which is a separate book by the same author.VMM is probably as close to a 'canned' (i.e. pre-built) testbench environment as you can get.If you run Synopsys VCS in your company, then VMM is worth investigatation.Unfortunately, I've heard it doesn't run well on competing simulators (Cadence, Mentor), as Systemverilog support is still in its infancy. ... Read more

Book Description

The exponential increase in transistor density on computer chips, supporting Moorer four decades, poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available.

Book Description

Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task.

Customer Reviews (1)

Excellent to learn SystemVerilog with OOP concepts
There are other couple of SV verification books in the market which teaches more on systemverilog syntax but this is the right book which teaches you the OOP concepts and how they are applied in System Verilog.. I strongly recommend for all verification engineers who want to get max out of SV language. It has very good examples also. ... Read more